1. Field
Exemplary embodiments of the present invention relate to a latch circuit and a latch circuit array including the same.
2. Description of the Related Art
Latch circuits for storing data are one of the most widely used circuits in semiconductor devices. As the degree of integration of semiconductor devices increases, capacitance at the storage node of latch circuits is reduced. Therefore, there are more soft errors, when data stored in the storage node of the latch circuit changes unintentionally. Soft errors are a phenomenon in which data stored in the latch circuit changes due to cosmic rays, such as alpha particles.
Latch circuits that are resistant to soft errors have been suggested. The latch circuit that best represents this is a latch circuit called a dual interlocked storage cell (DICE), published in [Calin et al., “Upset Hardened Memory Design for Submicron CMOS Technology”, IEEE Transactions on Nuclear Science, Vol. 43, No. 6 December 1996.].
FIG. 1 illustrates a configuration of the latch circuit published in the paper.
Referring to FIG. 1, the latch circuit includes first to fourth storage nodes SN1 to SN4, first to fourth transistor pairs 110, 120, 130, and 140, and a connection unit 150.
The first to fourth transistor pairs 110 to 140 include respective PMOS transistors 111 to 141 and NMOS transistors 112 to 142 that are connected in series through the respective storage nodes SN1 to SN4. Each of the storage nodes SN1 to SN4 is connected to a gate of an NMOS transistor of a transistor pair in a previous stage and a gate of a PMOS transistor of a transistor pair in a next stage. For example, the storage node SN2 is connected to the gate of the NMOS transistor 112 of the first transistor pair 110 in the previous stage and the gate of the PMOS transistor 131 of the third transistor pair 130 in the next stage.
The connection unit 150 includes four NMOS transistors 151 to 154. The NMOS transistors 151 to 154 are turned on when a selection signal SEL is activated, thus electrically connecting a data line D with the storage nodes SN2 and SN4 and electrically connecting an inverse data line DB with the storage nodes SN1 and SN3. The storage nodes SN2 and SN4 and the storage nodes SN1 and SN3 have opposite polarities.
The latch circuit of FIG. 1 has very strong immunity against soft errors generated due to cosmic rays. Data stored in the latch circuit may remain intact without an error unless data stored in two or more of the storage nodes SN1 to SN4 are changed due to cosmic rays. For example, although data stored in the storage node SN1 is changed from a logic high level ‘H’ to a logic low level ‘L’ due to a cosmic ray when data of logic levels ‘H’, ‘L’, ‘H’, and ‘L’ have been stored in the respective storage nodes SN1, SN2, SN3, and SN4, the data stored in the storage node SN1 may change from a logic low level ‘L’ to a logic high level ‘H’ again due to the PMOS transistor 111. That is, in the latch circuit of FIG. 1, soft errors are not generated unless the data stored in two or more storage nodes are changed due to cosmic rays since the probability that the data stored in two or more storage nodes will change is very low.
When the connection unit 150 connects the storage nodes SN1 to SN4 with the data lines D and DB, the latch circuit transfers data from the data lines D and DB to the storage nodes SN1 to SN4 during a write operation, and transfers data from the storage nodes SN1 to SN4 to the data lines D and DB during a read operation. That is, when the data lines D and DB have strong a driving force, a write operation is performed on the latch circuit. When the data lines D and DB have a weak driving force, a read operation is performed on the latch circuit. However, even in the read operation, data stored in the latch circuit may be lost because data stored in the storage nodes SN1 to SN4 are inverted due to charges remaining the data lines D and DB.